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19-0324; Rev 2; 12/97
1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection
________________General Description
The MAX3262 limiting amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 1Gbps. The amplifier's gain can be adjusted between 33dB and 48dB. At maximum gain, signals as small as 6mVp-p can be amplified to drive devices with PECL inputs. The MAX3262 has complementary loss-of-signal outputs for interfacing with open-fiber-control (OFC) circuitry. These outputs can be programmed to assert with input levels between 9mVp-p and 48mVp-p. LOS hysteresis for any programmed level is nominally 3.0dB, preserving a balance between noise immunity and dynamic range.
____________________________Features
o 900MHz Bandwidth o 48dB Maximum Gain o Chatter-Free LOS o Programmable LOS Threshold o Single +5V Power Supply o Fully Differential Architecture
MAX3262
_______________Ordering Information
PART MAX3262CAG MAX3262C/D TEMP. RANGE 0C to +70C (TA) 0C to +100C (TJ) PIN-PACKAGE 24 SSOP Dice*
________________________Applications
1062Mbps Fibre Channel 622Mbps SONET
Pin Configuration appears at end of data sheet.
*Dice are designed to operate over this range but are tested and guaranteed only at TA = +25C.
____________________________________________________Typical Operating Circuit
CAZ
CZP CZN FILTER CIN DIN+
MAX3260
INPUT OUTPUT DINVCC GND 50 +5V +5V C1 0.01F VCCA VCCB VCCC VCCD VCCE VCC CIN ENB
DOUT+
RECEIVER WITH PECL TERMINATIONS (50 TO VCC - 2V)
MAX3262
DOUT-
LOS +5V LOSB
VLOS
GND
DIV2
R 4.7k
R 4.7k LOS
+5V C1 0.01F +5V R1 R2
LOSB
________________________________________________________________ Maxim Integrated Products
1
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1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection MAX3262
ABSOLUTE MAXIMUM RATINGS
Power Supply, VCC - VEE ......................................................6.0V Input Voltage, DIN+, DIN- .....................................................6.0V CZN, CZP, ENB, VLOS, DIV2, LOS+, LOS-.....-0.3V, VCC + 0.3V DOUT+, DOUT- (with 50 load) .......................2.5V, VCC + 0.3V Continuous Power Dissipation (TA = +70C) SSOP (derate 10mW/C above +70C) ....................500mWC Junction Operating Temperature ......................-55C to +150C Storage Temperature Range .............................-55C to +175C Processing Temperature (Die).........................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +5V, RLOAD = 50 to VCC - 2V (equivalent), TA = 0C to +70C. Typical values are at VCC = 5V and TA = +25C.) PARAMETER Power-Supply Current Enable Input Current VLOS Input Current Common-Mode Output Voltage LOS+, LOS- Output Low Voltage DIV2 Short-Circuit Current Differential Output Offset, DOUT+ to DOUTInput Bias Voltage VDIN 2.5 SYMBOL IVCC IENB ILOS VCC = 5.0V IOUT = -1.0mA DIV2 = 0V 0.5 35 3.0 3.5 120 3.7 3.8 0.5 No output load CONDITIONS MIN TYP MAX 60 150 UNITS mA A A V V mA mV V
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V, RLOAD = 50 to 3V, AC parameters are not tested, TA = +25C, unless otherwise noted.) PARAMETER Power-Supply Rejection Ratio LOS Release Time, Minimum Input LOS Release Time, Maximum Input LOS Assert Time Input Voltage Range LOS Sensitivity Range LOS Hysteresis Differential Input Noise Pulse-Width Distortion Output Edge Speed Output Voltage Amplitude Small-Signal Bandwidth SYMBOL PSRR tOFFL tOFFH tONL VID VSR HYS Vn PWD tR, tF VOUT BW VOH - VOL MAX3262C/D MAX3262CAG 400 800 750 600 925 810 CONDITIONS Input referred, 55MHz (Note 1) (Note 2) (Note 1) Peak-to-peak Differential inputs, peak-to-peak MAX3262C/D MAX3262CAG 0.006 9 10 1.5 3.0 80 40 250 730 0.2 0.020 MIN TYP 35 0.5 0.5 0.5 1.8 48 48 5.0 MAX UNITS dB s s s V mV dB V ps ps mV MHz
VLOS = 5V, Pattern 27 - 1PRBS VLOS = 5V, DIV2 = GND (Note 3) 1Gbps, 8mVp-p input
Note 1: Input is a 200MHz square wave, tR < 300ps, 8mVp-p. Note 2: Input is a 200MHz square wave, tR < 300ps, 1.8Vp-p. Note 3: Input-referred noise = RMS output noise/low-frequency gain. 2 _______________________________________________________________________________________
1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection
__________________________________________Typical Operating Characteristics
(VCC = 5V, TA = +25C, unless otherwise noted.)
VCC SUPPLY CURRENT (NO OUTPUT LOAD) vs. TEMPERATURE
MAX3262-01
MAX3262
LOS HYSTERESIS vs. TEMPERATURE
MAX3262-02
LOS SENSITIVITY vs. FREQUENCY
7.5 SENSITIVITY (mVp-p) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 PRBS 27-1 K28.5 SEQUENCE (FIBRE CHANNEL IDLE PATTERN) 1-0 PATTERN
MAX3262-03
70 65 SUPPLY CURRENT (mA) 60 55 50 45 40 0 5.25V
8 1Gbps WITH 1,0 PATTERN 7 6 HYSTERESIS (dB) 5 4 3 2
8.0
5.0V 4.75V
1 0
10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
0
20
40
60
80
100
120
400
600
800
1000
TEMPERATURE (C)
FREQUENCY (Mbps)
LOS HYSTERESIS vs. VLOS
1Gbps DIV2 = 0 1,0 PATTERN
MAX3262-04
FREQUENCY RESPONSE
VLOS = 5V DIV2 = GND VLOS = 5V DIV2 OPEN VLOS = 3.4V DIV2 OPEN 37
VLOS = 3.0V DIV2 OPEN
MAX3262-05
5.0 4.0 HYSTERESIS (dB)
55
49 43
2.0
GAIN (dB)
3.0
1.0
31
0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 VLOS (V)
25 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz)
EYE DIAGRAM
MAX3262-07
1Gbps RLOAD = 50 to VCC - 2V (EQUIVALENT) VIN = 250mV, VCC = +5V, DIV2 = GND, VLOS = VCC
100mV/div
VLOS = VCC -500mV 225ps/div 2s/div
_______________________________________________________________________________________
MAX3262-06
+500mV
LOS OPERATION
LOS OUTPUT
DATA INPUT
3
1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection MAX3262
_____________________________________________________ __________Pin Description
PIN 1 2 3 NAME VCCB VLOS CZP Positive supply for internal gain stages Power detect/LOS level set. Use this input to program the required threshold level for LOS assertion. Offset-correction loop compensation capacitor. This pin should be connected to the CZN pin through a 100nF to 330nF capacitor, which provides the dominant pole for the offset-correction loop. Offset-correction loop compensation capacitor. This pin should be connected to the CZP pin through a 100nF to 330nF capacitor, which provides the dominant pole for the offset-correction loop. Power supply for the input stage amplifier Data Input Inverting Data Input Ground for the input stage amplifier Output Enable. Output gain stage is disabled and LOS circuitry remains functional. Input stage gain adjust. Grounding this pin forces the input stage gain to maximum (11dB) for applications where the LOS threshold level will be set for input signals in the 9mVp-p to 20mVp-p range. Leaving this pin open forces the gain of the input stage to be divided by two (6dB) for applications where the LOS threshold level will be set for input signal levels in the 15mVp-p to 48mVp-p range. Comparator threshold voltage for test only. Leave unconnected. Positive supply for the power detect/LOS circuitry Ground for the power detect/LOS circuitry Ground for the LOS+/LOS- buffer circuitry Positive supply for the LOS+/LOS- buffer circuitry Loss-of-Signal detect. This pin is asserted low when input power drops below the LOS threshold level. Loss-of-Signal detect. This pin is asserted high when input power drops below the LOS threshold level. Inverting Data Output Data Output Substrate Ground Positive supply for bias generators Ground for bias generators Positive supply for output buffers Ground for internal gain stages FUNCTION
4 5 6 7 8 9
CZN VCCA DIN+ DINGND ENB
10
DIV2
11 12 13 14 15 16 17 18 19 20 21 22 23 24
VTH VCCE GND GND VCCD LOSLOS+ DOUTDOUT+ GND VCCC GND VCC GND
4
_______________________________________________________________________________________
1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection MAX3262
CAZ VLOS
OFFSET CORRECTION 20k DIN+ 5dB/11dB DINRMS DETECT BIAS 0dB to 11dB 10dB 10dB 6dB DOUTENB 20k DOUT+
DIV2
MAX3262
REFERENCE
LOS+ LOS-
Figure 1. Functional Diagram
_______________ Detailed Description
The MAX3262 is an integrated limiting amplifier intended for high-frequency fiber-optic applications. The circuit connects to typical transimpedance amplifiers found within a fiber-optic link. The linear signal output from a transimpedance amplifier can contain significant amounts of noise, and may vary in amplitude over time. The MAX3262 limiting amplifier quantizes the signal, and outputs a voltage-limited waveform over a 48dB input dynamic range. The MAX3262 provides an offset correction function that effectively reduces the offset voltage to negligible levels. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is partially removed by the offset correction function. An external capacitor is required between CZP and CZN to compensate the offset correction loop, determining the lower 3dB point.
Loss-of-Signal Function
The MAX3262 incorporates a chatter-free loss-of-signal function, which is used to detect that the input signal has dropped below the level necessary for acceptable bit error rate performance, or to indicate an open-fiber condition. The loss-of-signal function is implemented with a rectifying peak detector, which samples the signal entering the output stage. The output from the peak detector is compared against an internally generated threshold, and is used to assert the LOS+ and LOSoutputs. The loss-of-signal threshold is adjusted by varying the amplifier gain. The MAX3262 is configurable for gains between 33dB and 48dB, allowing LOS thresholds between 9mVp-p and 48mVp-p. Figure 2 shows the LOS threshold as a function of the DIV2 and VLOS pins. The DIV2 pin provides a coarse adjustment of 6dB of gain, while the VLOS pin provides a fine gain adjustment between 0dB and 11dB.
_______________________________________________________________________________________
5
1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection MAX3262
LOS ASSERT LEVEL
45 40 SENSITIVITY (mVp-p) 35 30 25 20 15 10 5 0 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 RLOS 3.3k VLOS (V) DIV2 GROUNDED LOS BUFFER CLOS DIV2 OPEN VCC = 5V
MAX3262-07
50
+5V
MAX3262
LOS+
RLOS LOS OUTPUT WITH DESIRED RISE TIME
Figure 2. MAX3262 Sensitivity vs. VLOS Setting
Figure 3. Setting the LOS Time Constant
Level-detect hysteresis and a 200ns internal delay ensure chatter-free LOS outputs when the input signal level is close to the LOS threshold. The hysteresis for any programmed loss-of-signal level is nominally 2.5dB. The LOS+ and LOS- outputs are open-collector, Schottky-clamped transistors, that require pull-up resistors for proper operation (Figure 3). The loss-of-signal time constant is set externally with the appropriate pull-up resistor and shunt load capacitance. The ENB pin allows the user to disable the output signal without removing the input signal.
Wire Bonding Die
For reliable operation, the MAX3262 has gold metalization. Connections to the die should be made with gold wire only, using ball bonding techniques. Wedge bonding is not recommended. Bond pad size is 4 mils.
CIN should be large enough to not affect the signal quality, but small enough to not affect the LOS assert time. When an open-fiber condition occurs, the input coupling capacitors must discharge below the LOS threshold level before the LOS can assert. The worstcase discharge time would occur with the maximum input signal and the minimum LOS threshold. In this case, the input capacitor must discharge from 0.9V to 4.5mV. The time required for this to occur is: t = (1500)(CIN) In(VMAX / VTHRESH) seconds Example: If the MAX3262 is configured for 6mV sensitivity, CIN = 100pF results in a lower -3dB frequency of 1MHz, and a maximum LOS delay of about 1s. The offset correction capacitor (CAZ) must be greater than 100nF to ensure stable operation. This capacitor is in series with an internal 40k of resistance. The -3dB point of the offset zeroing circuit is: 1 / [(2)(CAZ)(40k)] Hz For CAZ = 180nF, the bandwidth of the offset correction circuit is 22Hz. Maxim's proprietary offset-correction architecture decouples the input coupling time constant from the offset correction time constant. This ensures there is no interaction between these two networks, eliminating an additional source of chatter on LOS.
__________________ Design Procedure
Determining Capacitor Values
The MAX3262 inputs must be AC coupled to allow proper operation of the offset correction function. Figure 4 shows the circuit's input stage. The circuit's lower -3dB point is determined by the input coupling capacitors. The lower -3dB frequency is 1 / [(2)(1500)(CIN)] Hz.
6
_______________________________________________________________________________________
1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection
Output Termination
The MAX3262 outputs must be terminated with a 50 load to (VCC - 2V), or a Thevenin equivalent. Figure 5 shows two possible output termination methods.
MAX3262
VCC
MAX3262
Layout and PC Board Design
CIN VIN CIN DINDIN+
1.5k
1.5k
Since the MAX3262 is a high-frequency component, the circuit's performance can largely be determined by board layout and design. A common problem with high-gain amplifiers is feedback from the large swing outputs to the input via the power supply. Some fiberoptic limiting amplifiers suffer from LOS "chatter." The act of switching the LOS outputs on or off generates noise on the power supply, which can cause the LOS outputs to chatter. With proper board layout, the MAX3262 ensures chatter-free LOS operation. The MAX3262 has five ground pins and a substrate connection. All of these should be connected to the circuit board's ground. Use multiple PCB vias close to the part to connect the grounds. Avoid long, inductive runs, which can degrade MAX3262 performance. The MAX3262's six VCC supply pins must all be connected. VCCA-VCCE can be collectively decoupled with one capacitor. VCC (pin 23) should be decoupled separately (see the Typical Operating Circuit).
Figure 4. MAX3262 Equivalent Input Circuit
+5V 82 DOUT+ 330 50 DOUT+ 120
MAX3262
MAX3262
+5V 82
ZLOAD >500
DOUT330 50
DOUT120
a) DRIVING A 50 LOAD TO GROUND
b) DRIVING A HIGH-IMPEDANCE LOAD
Figure 5. Output Termination Techniques
_______________________________________________________________________________________
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1Gbps, High-Speed Limiting Amplifier with Chatter-Free Loss-of-Signal Detection MAX3262
___________________Pin Configuration
TOP VIEW
VCCB 1 VLOS 2 CZP 3 CZN 4 VCCA 5 DIN+ 6 DIN- 7 GND 8 ENB 9 DIV2 10 VTH 11 VCCE 12 24 GND 23 VCC 22 GND 21 VCCC
____________________Chip Topography
GND DOUTLOSDOUT+ LOS+
V CC C
GND
V CC D
MAX3262
20 GND 19 DOUT+ 18 DOUT17 LOS+ 16 LOS15 VCCD 14 GND 13 GND
V CC
GND 0.080" (2.032mm)
GND
GND
V CC B
V CC E
SSOP
V LOS
VTH
CZP
DIV2
CZN
V CC A DIN+ DIN- GND 0.060" (1.524mm)
ENB
TRANSISTOR COUNT: 200 SUBSTRATE CONNECTED TO GND PIN 17
Maxim makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Maxim assume any liability arising out of the application or use of any product or circuit, and Maxim specifically disclaims any and all liability including, without limitation, consequential or incidental damages. "Typical'' parameters can and do vary in different applications. All operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. Maxim products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Maxim product could create a situation where personal injury or death may occur.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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